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CPLD Registers
7
6
5
4
3
2
1
0
R
IRQ3
IRQ2
IRQ1
IRQ0
—
—
—
—
W
Reset:
—
—
—
—
0
0
0
0
Figure 7-15. Interrupt from DSP Status Register (ISR)
Table 7-12. ISR Bit Descriptions
Bits
7–4
Name
IRQ[3–0]
Description
Interrupt request from DSP[3–0]. Shows the interrupt 0
status from each MSC711x device. The Event2 pin
1
Settings
Requesting interrupt.
Not requesting interrupt.
from each MSC711x device signals interrupts to the
host.
3–0
—
Reserved. Cleared to zero for future compatibility.
7
6
5
4
3
2
1
0
R
IE3
IE2
IE1
IE0
—
—
—
—
W
Reset:
0
0
0
0
0
0
0
0
Figure 7-16. Interrupt from DSP Enable Register (IER)
Table 7-13. IER Bit Descriptions
Bits
Name
Description
Settings
7–4
IE[3–0]
Interrupt request from DSP[3–0] enable. Determines
whether an IRQ signal from an MSC711x device is
0
1
Request is disabled.
Request is enabled.
used to signal the global active low IRQ signal to the
host.
3–0
—
Reserved. Cleared to zero for future compatibility.
Note: The CPLD firmware is written to enable/disable the IRQ signals properly when they are configured as active low out of
the MSC711x devices. If only one device is enabled at a time, the signal polarity does not matter.
7
6
5
4
3
2
1
0
R
BV1
BV0
MV2
MV1
MV0
mV2
mV1
mV0
W
Reset:
—
—
—
—
—
—
—
—
Figure 7-17. Firmware Version Register (FVR)
MSC711x Packet Telephony Farm Card (SPT711xPFCE), Rev. 1
28
Freescale Semiconductor
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